1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a transistor and fabrication method for forming such a transistor in which a first source/drain region is formed below a second source/drain region such that the transistor channel has a vertical component.
2. Description of Relevant Art
Universal fabrication of field-effect transistors is well known. The manufacturing process begins by lightly doping a single crystal silicon substrate with an ntype or p-type impurity. The specific area where the transistor will be formed is then isolated from other areas on the substrate with the use of isolation structures. In modern fabrication laboratories, the isolation structures may comprise shallow trenches in the substrate filled with a dielectric such as oxide to insulate the transistors from one another. Isolation structures may alternatively comprise, for example, local oxidation of silicon ("LOCOS") structures which are well known in the art. A gate dielectric may be formed by thermal oxidation of the silicon substrate. The gate structure is then patterned after depositing a layer of polycrystalline silicon ("polysilicon") over the gate dielectric. Subsequently, the polysilicon and the source and drain regions are doped, via ion implantation, with an n-type or p-type dopant. When voltage above a certain threshold is applied to the gate, the channel between the source and drain regions becomes conductive and the transistor turns on.
The operating characteristics of field-effect transistors fabricated with standard metal-oxide-semiconductor ("MOS") integrated circuit techniques are a function of the transistor's dimensions. In particular, the source-to-drain current (I.sub.ds) is proportional to the ratio of the transistor's width (W) to the transistor's length (L). For given transistor width and a given biasing condition (e.g. V.sub.G =3V, V.sub.D =3V, and V.sub.s=OV), I.sub.ds is maximized by minimizing the transistor length L. Minimizing transistor channel length also improves the speed of integrated circuits comprised of a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from a device operation standpoint. In addition, minimizing the transistor length L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases and, with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon.
The main limitation of minimum device size in a conventional transistor fabrication process is the resolution of the optical lithography printing system. In an optical lithography printing system, radiation is directed from an illumination source through a patterned mask and onto a photoresist layer. The patterned mask transmits the illumination source radiation onto selected areas of the photoresist layer to reproduce the mask pattern in the photoresist layer. Resolution in optical lithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, there is a minimum distance beyond which even a geometrically perfect lens cannot resolve two points. In other words, when two points are less than a minimum distance from each other, the two points cannot be resolved by the lithography system. The diffraction patterns associated with each point overlap each other to such an extent that the two points cannot be effectively differentiated. The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleighs criteria defines two images as being resolvable when the intensity between them drops to 80% of the image intensity. This criteria is satisfied when the 2d=0.61.lambda./NA. Where 2d is the separation distance of two images, .lambda. is the wavelength of the energy source, and NA is the numerical aperture of the lens.
Commercially available optical photolithography machines are typically equipped with mercury vapor lamps as the illumination source. The characteristic energy spectrum of a mercury vapor lamp contains several distinct peaks in the 300nm to 450nm wavelength range. These peaks are commonly referred to by their industry designations. The peak associated with a wavelength of .about.436nm is designated the "G-line," the .about.405nm peak the "H-line," and the .about.370nm peak the "I-line." Photolithography aligners are similarly designated such that it is common to speak of "G-line aligners." The minimum feature size resolvable by a G-line aligner is greater than the minimum feature size of an I-line aligner because of the longer G-line wavelength.
As process technologies approach and surpass the resolvable limits of G-line and I-line aligners, semiconductor manufacturers are typically forced to implement alternative photolithography techniques to achieve adequate resolution of the minimum features. Unfortunately, the conventional alternatives involve abandoning or substantially modifying the existing photolithography equipment at a prohibitive cost. In addition to the capital required to purchase and install the improved equipment, there are extensive costs associated with qualifying the new equipment for production worthiness and training production and maintenance personnel in the operation and care of the new equipment. Therefore, it is highly desirable to design an MOS transistor and a transistor fabrication process in which the transistor channel length is not limited by the capabilities of the photolithography equipment.